Introduction to Sequential Logic: CMOS D-Latch/Flip-Flop Schematic and Simulation
This lab focuses on understanding and building basic memory circuits, specifically the CMOS D-Latch and D-Flip-Flop. Students explore the differences between sequential and combinational logic, learn about key timing rules such as setup time and hold time, and address issues like metastability in digital systems. The practical aspect includes drawing and simulating circuits, measuring performance, and analyzing results to ensure correct operation under specified conditions.
Sections
Navigate through the learning materials and practice exercises.
What we have learnt
- Sequential logic circuits retain memory and their output depends on both current inputs and previous states.
- Understanding timing rules such as setup time, hold time, and clock-to-output delay is crucial for reliable memory circuit functionality.
- Metastability can arise when timing conditions are not adequately met, potentially leading to system failure.
Key Concepts
- -- Sequential Logic
- Types of circuits that have memory and whose outputs depend on current inputs and previous states.
- -- DLatch
- A memory device that captures input data and maintains its value while the clock signal is low.
- -- DFlipFlop
- An edge-triggered memory device that changes its output only at specific moments during the clock signal transitions.
- -- Setup Time (t_setup)
- The minimum time before the clock edge that an input must be stable to guarantee proper operation.
- -- Hold Time (t_hold)
- The minimum time after the clock edge that the input must remain stable to ensure the output is correctly captured.
- -- ClocktoOutput Delay (t_CQ)
- The time taken for the output to reflect a change after the clock signal activates.
- -- Metastability
- A state where the flip-flop is uncertain between output states due to violations of timing requirements.
Additional Learning Materials
Supplementary resources to enhance your learning experience.