29.4.2. Components of a Typical DMA Controller

In case of interrupt driven I/O, there is a change of context. In case of DMA transfer, there is no context change; the context of the processor remains the same, whatever program it is executing.

This chunk introduces the fundamental difference between interrupt-driven I/O and Direct Memory Access (DMA). In interrupt-driven I/O, when an interrupt occurs, the CPU stops its current task and switches context to handle the interrupt. This context switch can slow down processing. On the other hand, DMA allows peripherals to access memory without interrupting the CPU. This enables the CPU to continue executing its tasks while data is transferred in the background.

Think of it like a waiter in a restaurant (CPU) who can either stop all service to help a customer with a special request (interrupt-driven I/O) or however, they can keep serving other tables while a kitchen assistant (DMA) prepares an order without needing the waiter's immediate attention.

CPU is suspended just before it accesses the bus. At that point, the DMA controller takes control of the bus to transfer data.

When DMA is in operation, the CPU will pause its activities just as it is about to use the system bus for data fetching or writing. This suspension allows the DMA controller to take over the bus and facilitate data transfer directly between memory and the I/O device, which prevents any context switching for the CPU.

Imagine a person who needs to pick up a package from the back of a delivery truck (the CPU needing data) but is momentarily blocked by another process. Instead of waiting to take the package, another team member can step in and take the package directly while the person continues with their other tasks.

Most processors have a buffer space consisting of an instruction buffer and a data buffer, allowing the CPU to execute instructions while DMA transfers occur.

The CPU often has two types of buffers: one for instructions and one for data. While DMA is transferring data, as long as there are instructions or data in these buffers, the CPU can continue executing instructions or processing data without having to wait for DMA operations to finish.

Consider a chef who is preparing a meal (CPU) while another staff member is setting the table (DMA). The chef can continue to chop vegetables (executing instructions) while the table is being set, as long as they have all necessary utensils at hand (buffers).

There are two main data transfer modes in DMA: burst transfer mode and cycle stealing mode.

In burst transfer mode, DMA transfers all data at once, for example, transferring 1000 bytes in one go, and then signals the CPU when finished. Conversely, in cycle stealing mode, the DMA transfers data one byte at a time and gives control back to the CPU in between transfers, allowing the CPU to perform other tasks more frequently, but potentially extending the overall transfer time.

Think of burst mode as filling a bucket with water all at once, while cycle stealing mode is like filling a glass of water drop by drop. The first method is faster, but the second allows for other activities to continue while you fill the glass.

The DMA controller can be connected to the CPU and memory via a single bus setup, or through various configurations which influence how control of the bus is managed during data transfers.

The configuration of how DMA connects to the CPU and memory can affect efficiency. A single bus means that DMA and CPU must share access, which can cause delays. Other configurations may allow DMA to control the bus exclusively, reducing CPU suspension time.

Picture a one-lane road (single bus configuration) where cars (DMA requests) must wait their turn to pass. If there were a multi-lane highway (multiple configurations), cars could zoom past without waiting as much, making the journey smoother for everyone.

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