29.1. Overview of DMA and Interrupt Driven I/O

In case of interrupt driven I/O, there is a change of context. In case of DMA transfer, there is no context change; the context of the processor remains the same whatever program it is executing.

In interrupt-driven I/O, when an interrupt occurs, the CPU stops its current task, saves its context (like registers and program counter), and switches to handle the interrupt. This means it has to change its current operation and context to address the interrupt, resulting in context switching. However, in a Direct Memory Access (DMA) transfer, the CPU continues executing its current program without context switching. The DMA controller takes control of the system bus to transfer data directly from memory or to memory with the processor remaining unaffected.

Think of a chef (the CPU) who is cooking (executing a program). If someone calls for the chef's attention (an interrupt), the chef must stop cooking, note down where they were, and help with the request first. This is similar to interrupt-driven I/O. In contrast, if a helper (the DMA controller) starts taking care of another dish (data transfer) without disturbing the chef, the chef can continue cooking. This is like how DMA works.

CPU is suspended just before it accesses the bus... DMA controller... Now processor cannot access the main memory.

When the CPU needs to perform an operation that requires data from memory, it is supposed to access the system bus. However, during a DMA operation, the DMA controller has control of the bus, preventing the CPU from accessing the main memory for the needed data. This means the CPU must pause or suspend its current task until the DMA transfer is complete. It can’t do any other work that requires accessing the main memory because it simply doesn’t have the bus available to it.

Imagine a team of people working on different projects. If one person (the DMA) is given access to a bulk of materials (data from memory), the rest of the team (CPU) must wait until the materials are delivered before they can continue with their own tasks.

...most of the processor we are having a buffer space. In the buffer space again two type of buffers we are having: we are having instruction buffer and we are having a data buffer...

Modern processors include buffering capabilities, which help in storing instructions and data temporarily. When DMA is in progress, if the processor already has some instructions in the instruction buffer and data in the data buffer, it can continue executing the already fetched instructions while waiting for the DMA transfer to complete. The processor will have to suspend activity when it needs to access the memory again for more instructions or data during the DMA operation.

Think of this as having a waiting room in a doctor's office. While the doctor (processor) is treating patients (executing instructions), staff (DMA) can prep for the next schedules by fetching files (data). If a patient needs to provide new medical history (data), the doctor must pause until the staff returns with that information.

What are the data transfer mode? there is two way of transferring the information; one is called burst transfer mode and second one is your cycle stealing mode.

DMA has different modes for transferring data. In burst transfer mode, the DMA controller takes control of the bus and transfers all the data in one continuous sequence. For instance, if it needs to move 1000 bytes, it will do this all at once before returning control back to the CPU. Conversely, in cycle stealing mode, the DMA controller transfers data piece by piece, allowing the CPU to interleave its operations with the DMA transfers. This is slower but enables the CPU to continue working without a long pause.

Imagine a delivery truck. In burst mode, the truck would unload all packages at once before leaving (like transferring all data in one go). In cycle stealing, the truck makes several trips, offloading just a few packages at a time but allowing the office workers (CPU) to continue their work while the truck is in and out.

This is the interrupt process cycle... it will execute a complete instruction and then it will check for the interrupt.

When the CPU is executing a program, it routinely checks for interrupts. An interrupt breakpoint occurs when the CPU completes a current instruction and pauses to determine if there’s any interrupt that needs to be handled. This is crucial as it allows the CPU to address urgent tasks without abandoning its current instruction flow too abruptly.

Think of a teacher in a classroom who finishes a lesson (instruction). After completing the lesson, the teacher pauses to listen to any student who raises their hand (interrupt). This ensures that important questions or issues can be addressed immediately after a topic is wrapped up.

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