29.1.3.2. Cycle Stealing Mode

In case of DMA transfer, there is no context change; the context of the processor remains the same whatever program it is executing. The CPU is suspended just before it accesses the bus.

DMA, or Direct Memory Access, allows certain hardware subsystems to access system memory independently of the CPU. Unlike interrupt-driven I/O, where the CPU must change context and manage the I/O operation itself, DMA does not require the processor to change its ongoing task. The CPU remains in its current operation while the DMA controller handles data transfer, only getting suspended briefly before accessing the bus.

Imagine you're working on a project and your friend is responsible for fetching materials for you while you work. You might need to take a short break to let them do their job, but overall, you're not changing your focus or context—you're still working on the project.

In most processors, there is a buffer space that includes both an instruction buffer and a data buffer. The processor can execute tasks stored in the buffer while DMA transfers data.

While the DMA is transferring data, the processor can utilize pre-fetched instructions and data stored in the instruction and data buffers, respectively. This allows for some level of continual processing by the CPU instead of it sitting idle waiting for the DMA transfer to complete. It can work on instructions that it has already buffered, hence optimizing CPU usage during the DMA process.

Consider a chef who has prepped ingredients ahead of time. Even if a friend is handling a boiling pot while they chop vegetables, the chef can still work efficiently by using the ingredients that are ready, saving time instead of waiting for everything to be done.

Burst transfer mode transfers the entire information in one go, while cycle stealing mode allows the DMA controller to 'steal' cycles from the CPU to transfer data intermittently during the operation.

In burst transfer mode, the DMA gets total control of the bus for the duration of the data transfer. It can efficiently manage large transfers but may leave the CPU idle for a longer time, waiting for it to regain control after the transfer. Cycle stealing mode mitigates this by allowing the CPU to interject at intervals, letting it carry out some tasks during the DMA's data transfer. This can slow down the CPU but maintains a level of processing efficiency.

Picture a delivery truck (DMA) that must unload a full shipment. In burst mode, the truck blocks a loading dock until all items are unloaded. In cycle stealing mode, the truck unloads an item, and then while it gathers the next item, the loading dock can serve another small delivery—ensuring the dock isn't completely idle.

When using cycle stealing mode, the access of the bus switches between the processor and DMA controller, allowing more balanced system performance, but may lead to a longer overall data transfer time.

Cycle stealing mode creates a situation where the processor can occasionally access the bus, which can decrease its performance slightly compared to burst mode since the DMA transfer will take longer overall. Despite this, it allows for active processing and better resource management within the system than simply waiting for the transfer to complete in burst mode.

It's comparable to a busy coffee shop where customers can place orders (processor) while a barista (DMA) brews coffee (data). If the barista only brews all at once without interruption, customers will wait longer. If the barista brews and serves in stages, customers get their drinks while others are still being made, increasing overall satisfaction, even if some customers have to wait a bit longer to finish brewing.

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