15.2.2. Comparing Indirect Modes

Now, we will go to the another mode, which is more complex in nature which is the indirect mode. By indirect mode already we mean that whenever it’s the indirect mode of 𝑀; that means, we say this is the memory here is 𝑀, at the address of 𝑀 here there may be some addresses called x is some content over here...

Indirect mode refers to a way of addressing where the instruction does not directly point to the data (the operand) but instead points to a memory location that contains the address of the operand. This method is called 'indirect' because it requires an additional step to retrieve the necessary data. In other words, when using indirect mode, a memory address is stored in another memory location, which must be accessed first to obtain the actual operand.

Think of indirect addressing like a treasure map where the 'X' marks the spot where the treasure is buried (the operand). Instead of directly marking the spot with the treasure, the map contains directions to another point that tells you where to dig. Just as you need to read the directions before finding the treasure, in indirect addressing, you need to access the memory location to find the final data.

So, if you now look at basically your first 3 stages. So, first 3 stages; as I already were discussing like 𝑃𝐶 out 𝑀𝐴𝑅 and this is control stage basically are only for fetching the instruction...

The first three stages involve crucial steps in fetching an instruction from memory. They include: 1) Program Counter (PC) which tracks the address of the next instruction to be executed; 2) Memory Address Register (MAR) which stores the address where the instruction is located; and 3) Control Logic which orchestrates this process. These stages must be completed to ready the CPU to execute the instruction contained at the specified memory address.

Imagine the CPU as a librarian. The librarian uses the Program Counter to determine the next book to pull from the shelf (the instruction). The Memory Address Register is like the catalog system in the library that tells the librarian where that book is located (the address in memory). The Control Logic acts as the librarian’s training, ensuring all steps and checks are followed correctly to fetch the right book.

So, the next stage is 𝐼𝑅 memory register in and read if we are fetching the basically... after executing the third instruction the third control step register instruction register IR is having the value of 𝐿𝑂𝐴𝐷 𝑅 , 𝑀...

Once the instruction is fetched, the Instruction Register (IR) holds the instruction that needs to be executed. In this case, the instruction is to load data from an indirect memory location. This means the CPU will first determine the address of the actual data by referencing the indirect memory address, executing necessary steps to convert this indirect reference into a direct useable operand stored in the register.

Continuing the librarian analogy, once the librarian finds a book using the catalog system (the MAR), they check the turning page of the book (the Instruction Register) to see what the book contains (the instruction). If it says 'look up table of contents' first before you start reading, the librarian now knows to search another section before delivering the book’s contents to you.

Of course, in stage 5 we have to wait till everything is ready... we actually say 𝐼𝑅...

In this stage, the CPU waits until the information is ready from memory before moving forward. The data at the indirect address is loaded into the Memory Data Register (MDR), which temporarily holds the fetched data. Only once this data is confirmed to be ready, does the CPU perform the necessary operations to transfer the data to the designated register for use.

This stage is like a restaurant where the waiter must wait for your food orders to be completed before serving it to you. Until the chef is done cooking the meal (the data is ready in the Memory Data Register), the waiter (CPU) cannot serve it to you (transfer it to the register). This ensures that you get your meal fresh and complete.

...so, if you quickly look at what it happens in the bus it will be more clear... in this case now it will be an 𝑥....

After the data is confirmed as ready in the MDR, it is transferred to the target register where it will be used for computation or further processing. The entire process of fetching an indirect operand generally requires careful stage management to ensure each part of the instruction is correctly executed without error.

Picture this final transfer as a relay race where each runner (stage) must pass the baton (data) accurately to the next runner (register) without dropping it. If the baton is dropped, then the race (instruction execution) cannot continue smoothly.

So, now, again another mode we are taking which is called registering indirect in this case...

Register indirect addressing is a type of indirect mode where the address of the operand is held in a CPU register instead of a memory location. This method increases speed as accessing registers is generally faster than accessing memory. The CPU reads the address from the register, uses it to fetch the operand from memory, and then performs necessary operations.

Think of register indirect addressing like using your smartphone to quickly look up a contact's address instead of searching through a physical address book. Accessing the phone’s memory (the register) is much faster than flipping through pages, just as registers provide quicker access to the data needed.

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