15.1.4. Memory Data Register Operations

Now, we will go to the another mode, which is more complex in nature which is the indirect mode. By indirect mode already we mean that whenever it’s the indirect mode of 𝑀; that means, we say this is the memory here is 𝑀, at the address of 𝑀 here there may be some addresses called x is some content over here, then again you have to look at the content in x and basically this is your operand, this is what is the idea we all know about it.

The indirect mode allows the CPU to access memory indirectly. In this mode, the instruction specifies a memory address (𝑀) that contains another address (x). The content at address x is the true source of the operand required for the instruction. This adds complexity, as the CPU must perform a dereference step to access the data needed for computation.

Imagine you're searching for a book in a library. Instead of looking directly for the book, you check the library catalog, which tells you that the book is located in a specific aisle. In this analogy, the library catalog represents the first memory address (𝑀), and the actual aisle where the book is found represents the second memory address (x).

So, if you now look at basically your first 3 stages. So, first 3 stages; as I already were discussing like 𝑃𝐶 𝑜𝑢𝑡 𝑀𝐴𝑅 and this is control stage basically are only for fetching the instruction.

The first three stages of processing involve fetching the instruction from memory. Here, the Program Counter (𝑃𝐶) outputs the address of the instruction which is then loaded into the Memory Address Register (𝑀𝐴𝑅). During these stages, the control stage manages the flow to ensure the correct instruction is fetched and prepared for execution.

Consider a chef preparing a meal. The chef first looks at a recipe (instruction) to know what ingredients (data) are needed. The chef's notes, where the recipe is written down, represent the stages in fetching the instruction.

Next one is what I have to do. So, this is the instruction load 𝑅 into memory from indirect memory location, that is the content of 𝑀 you have to again go to that memory location and there will get the operand it has to be loaded to 𝑅 that is we say that load the control memory location 𝑀1 to register 𝑅 where 𝑀1 is specified in the memory location that is indirect and we assume that the length is one.

After fetching the instruction, the next step is to execute it by loading the operand into a register. The CPU will check the indirect memory location specified by 𝑀, retrieve the operand, and place it into register 𝑅. This is done by sequentially accessing the memory twice: first to get to address x, and then to get the actual data stored at x.

Think of a scenario where you're at a restaurant. You order a dish (instruction), and the waiter (CPU) goes to the kitchen (memory) to fetch your order. First, the waiter finds out what you ordered (address), then checks how it's made (actual content) before bringing it to your table (register).

Now, the after executing the third instruction the third control step register instruction register IR is having the value of 𝐿𝑂𝐴𝐷 𝑅 , 𝑀. So, in the fourth stage what I am going to do I am going to take the value of 𝑀 and I am going to feed it into the memory address register so that you can read the value of memory location 𝑀 that is x in this example.

In this step, the instruction register IR which holds the instruction ‘LOAD R, M’ plays a critical role. The value of memory address M is then transferred to the Memory Address Register (MAR) to prepare for fetching the actual data. This separation of tasks ensures the CPU systematically loads the needed data.

Imagine putting on a virtual reality headset (instruction) that directs you to a specific location (memory address). You need to identify where that location is before you can actually 'go there' and see what's there (fetch the data).

So, once it is ready basically we know that the value of memory location 𝑀 that is 𝑥 in the example is now loaded into the memory data register now interestingly for all cases what we have seen for most of the cases after the memory data out, if it’s a direct instruction we generally take this memory data out from the memory buffer register we actually say 𝐼𝑅 , if is a fetch or sometimes we call 𝑅 in that way.

After loading the data from memory, the content is placed into the Memory Data Register (MDR). This value can then be used for computation or stored elsewhere. In direct memory access, the data flows straightforwardly into the Instruction Register (IR) or other registers. However, in this scenario, it is more intricate since we feed the data back into the MAR for further use.

This is like a computer programmer first writing code (fetching data); the code is then saved onto a flash drive (memory data register). Then, if needed, the programmer can simply take the flash drive and load it into another device to execute it.

So, if you quickly look at what it happens in the bus it will be more clear. So, look at the bus. So, many times you have to refer to this diagram.

This chunk refers to using a 'bus' for data movement and shows how control signals direct the flow of data. The bus is a communication system that transfers data between components of a computer. For instructions that require indirect addressing, the flow of operation is crucial in determining how the final operand is retrieved from memory.

Picture a busy street (bus) where cars (data) need to reach different destinations (registers). The traffic lights (control signals) direct when cars can turn, stop, or go, ensuring everything flows smoothly without crashes.

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