2.3.4. Example: Simple AND Gate

Try these first

1. 1.

   What does the AND gate output when both inputs are true?

   Hint

   Recall the output conditions for the AND gate.

2. 2.

   In Verilog, what keyword is used to define inputs?

   Hint

   Think about module definitions in Verilog.

3. 3.

   What does an AND gate output when both inputs are high?

   • True
   • False
   • Undefined

   Hint

   Consider the basic behavior of the AND gate.

4. 4.

   In Verilog, what is the purpose of the 'assign' statement?

   • True
   • False

   Hint

   Think about how outputs are calculated.

5. 5.

   Create a Verilog description for a circuit that combines two AND gates and one OR gate. Explain the expected output in various input scenarios.

   Hint

   Consider how combining logic gates can affect the final result.

6. 6.

   Write a testbench for the AND gate module that verifies its functionality for all possible input combinations.

   Hint

   How do you systematically verify each output state with your inputs?