2.3.2. Verilog Basic Structure

Try these first

1. 1.

   What does a module define in Verilog?

   Hint

   Think of it as a blueprint for the circuit.

2. 2.

   What is the purpose of the assign statement?

   Hint

   Recall how we created the output for an AND gate.

3. 3.

   What is the primary role of a module in Verilog?

   • Define inputs and outputs
   • Store values
   • Control timing

   Hint

   Remember, a module is like the main structure.

4. 4.

   True or False: The always block only executes once.

   • True
   • False

   Hint

   Consider how it reacts to inputs.

5. 5.

   Design a module that implements a full adder using multiple always blocks, ensuring to address carry inputs and outputs.

   Hint

   Focus on how to handle both sum and carry out.

6. 6.

   Explain how race conditions can occur within always blocks. Provide an example scenario.

   Hint

   Think of two people attempting to give a different instruction at the same time.